A Digital Design and Hardware Architecture for the HPRF Radar Signal Processor

Document Type : Original Article


1 Aeronautical University of Shahid Sattari, Tehran, Iran

2 Faculty of Electrical Engineering, Industrial University of Malek-e-Ashtar, Tehran, Iran


Today, the design and use of high-frequency repeater radars are very common because of the advantages of high power transmission and coping with extended clutters and jamming. However, it is always the design and implementation of digital processors that can handle system parameters such as the wide dynamic range above the input signal of these radar coverage has been challenging. In this paper, a method for digital design and determination of the hardware architecture of a high repetition frequency radar signal processor based on the use of software provided by Xilinx XSG It's easier to design and develop The FPGA-based chip-based is provided in the MATLAB Simulink software is presented, this method is based on the use of Software provided by Xilinx Inc. The results of hardware simulation and comparison of output blocks of processing blocks with the output of the analog blocks of the typical radar and comparison with analog digital combined hardware of general radars represent improvement dynamic range of input at least 70 dB and low weight of this processor for a radar with high pulse repetition frequency.


Main Subjects

[1] G. W. Stimson, Introduction to Airborne Radar, 2nd Edition, SciTech,1998.
[2] Virtex-6 FPGA User Guide, [Online], Available: http://www.xili-nx.com/support/documentation/user_guides/ug07.pdf.
[3] M. I. Skolnik, Radar Handbook, 2nd Edition, Mc GrawHill, 1990.
[4] M. A. Richards, J. A.Scheer, W. A. Holm; Principles of Modern Radar(Basic Principles), SciTech, 2010.
[5] A. Antey, Illumination and Guidance Radar Technical Description, 1993.
[6] J. H. J. Ballagh, “Building Custom FIR Filters Using System    Generator,” In Proc. 12th International Field-Programmable Logic and Applications Conference (FPL), Montpellier, France, p. 2438, 2002.
[7] Y. H. Hu, “CORDIC-based VLSI architectures for digital signal processing,” IEEE Signal Processing Magazine, vol. 9, pp. 16-35, 1992.